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ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram 28h4724 sa14-4221-06 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 31 features ? 2,097,152 word by 8 bit organization ? single 3.3v 0.3v or 5.0v 0.5v power supply ? standard power (sp) and low power (lp) ? 2048 refresh cycles - 32 ms refresh rate (sp version) - 128 ms refresh rate (lp version) ? high performance: -50 -60 units t rac ras access time 50 60 ns t cac cas access time 13 15 ns t aa column address access time 25 30 ns t rc cycle time 84 104 ns t hpc edo (hyper page) mode cycle time 20 25 ns ? low power dissipation - active (max) - 75 ma / 60 ma - standby: ttl inputs (max) - 1.0 ma - standby: cmos inputs (max) - 1.0 ma (sp version) - 0.1 ma (lp version) - self refresh (lp version only) - 200 m a (3.3 volt) - 300 m a (5.0 volt) ? extended data out (hyper page) mode ? read-modify-write ? ras only and cas before ras refresh ? hidden refresh ? package: tsop-ii 28 (400mil x 725mil) soj 28 (300mil) description the ibm0117805 is a dynamic ram organized 2,097,152 words by 8 bits, which has a very low sleep mode power consumption option. these devices are fabricated in ibms advanced 0.5 m m cmos silicon gate process technology. the circuit and process have been carefully designed to pro- vide high performance, low power dissipation, and high reliability. the devices operate with a single 3.3v 0.3v or 5.0v 0.5v power supply. the 21 addresses required to access any bit of data are multiplexed (11 are strobed with ras, 10 are strobed with cas). pin assignments (top view) 1 2 3 4 5 6 9 10 11 12 13 14 28 27 26 25 24 23 20 19 18 17 16 15 vss i/o7 i/o6 cas oe a9 a8 a7 a6 a5 a4 vss vcc i/o0 i/o1 we ras a10 a0 a1 a2 a3 vcc 7 8 i/o2 i/o3 nc i/o5 i/o4 22 21 pin description ras row address strobe cas column address strobe we read/write input a0 - a10 address inputs oe output enable i/o0 - i/o7 data input/output v cc power (+3.3v or +5.0v) v ss ground ibm01178052m x 811/10, 5.0v, edo. ibm0117805p2m x 811/10, 3.3v, edo, lp, sr. IBM0117805M2m x 811/10, 5.0v, edo, lp, sr. ibm0117805b2m x 811/10, 3.3v, edo. discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 31 28h4724 sa14-4221-06 revised 4/97 ordering information part number sp / lp self refresh power supply speed package notes ibm0117805t3 -50 sp no 5.0v 50ns 400mil tsop-ii 28 1 ibm0117805t3 -60 sp no 5.0v 60ns 400mil tsop-ii 28 1 ibm0117805bt3 -50 sp no 3.3v 50ns 400mil tsop-ii 28 1 ibm0117805bt3 -60 sp no 3.3v 60ns 400mil tsop-ii 28 1 IBM0117805Mt3 -50 lp yes 5.0v 50ns 400mil tsop-ii 28 1 IBM0117805Mt3 -60 lp yes 5.0v 60ns 400mil tsop-ii 28 1 ibm0117805pt3 -50 lp yes 3.3v 50ns 400mil tsop-ii 28 1 ibm0117805pt3 -60 lp yes 3.3v 60ns 400mil tsop-ii 28 1 ibm0117805j1 -50 sp no 5.0v 50ns 300mil soj 28 1 ibm0117805j1 -60 sp no 5.0v 60ns 300mil soj 28 1 ibm0117805bj1 -50 sp no 3.3v 50ns 300mil soj 28 1 ibm0117805bj1 -60 sp no 3.3v 60ns 300mil soj 28 1 IBM0117805Mj1 -50 lp yes 5.0v 50ns 300mil soj 28 1 IBM0117805Mj1 -60 lp yes 5.0v 60ns 300mil soj 28 1 ibm0117805pj1 -50 lp yes 3.3v 50ns 300mil soj 28 1 ibm0117805pj1 -60 lp yes 3.3v 60ns 300mil soj 28 1 1. sp = standard power version (ibm0117805 and ibm0117805b); lp = low power version (IBM0117805M and ibm00117805p) discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram 28h4724 sa14-4221-06 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 31 block diagram 11 11 11 10 10 8 8 8 8 8 a1 a2 a3 a4 a5 a6 a7 a10 a8 a9 2048 1024 x 8 cas ras we oe vcc vss & regulator (to ocds) v dd (internal) cas clock generator column address buffer (10) a0 refresh refresh counter (11) row address buffer (11) ras clock generator row decoder column decoder and i/o gate sense ampli?ers memory array 2048 x 1024 x 8 data in buffer data out buffer (5.0 volt version) controller i/o0 i/o7 discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 31 28h4724 sa14-4221-06 revised 4/97 truth table function ras cas we oe row address col address i/o0 - i/o7 standby h h ? x x x x x high impedance read l l h l row col data out early-write l l l x row col data in delayed-write l l h ? l h row col data in read-modify-write l l h ? ll ? h row col data out, data in edo (hyper page) mode read 1st cycle l h ? l h l row col data out 2nd cycle l h ? l h l n/a col data out edo (hyper page) mode write 1st cycle l h ? l l x row col data in 2nd cycle l h ? l l x n/a col data in edo (hyper page) mode read-modify-write 1st cycle l h ? lh ? ll ? h row col data out, data in 2nd cycle l h ? lh ? ll ? h n/a col data out, data in ras-only refresh l h x x row n/a high impedance cas-before- ras refresh h ? l l h x x n/a high impedance hidden refresh read l ? h ? l l h l row col data out write l ? h ? l l l ? h x row col data in self refresh (lp version only) h ? l llhx x x discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram 28h4724 sa14-4221-06 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 31 absolute maximum ratings symbol parameter rating units notes 3.3 volt device 5.0 volt device v cc power supply voltage -0.5 to +4.6 -1.0 to +7.0 v 1 v in input voltage -0.5 to min (v cc +0.5, 4.6) -0.5 to min (v cc +0.5, 7.0) v1 v out output voltage -0.5 to min (v cc +0.5, 4.6) -0.5 to min (v cc +0.5, 7.0) v 1 t opr operating temperature 0 to +70 0 to +70 c 1 t stg storage temperature -55 to +150 -55 to +150 c 1 p d power dissipation 1.0 1.0 w 1 i out short circuit output current 50 50 ma 1 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reli- ability. recommended dc operating conditions (t a = 0 to 70?c) symbol parameter 3.3 volt device 5.0 volt device units notes min. typ. max. min. typ. max. v cc supply voltage 3.0 3.3 3.6 4.5 5.0 5.5 v 1 v ih input high voltage 2.0 v cc + 0.5 2.4 v cc + 0.5 v 1, 2 v il input low voltage -0.5 0.8 -0.5 0.8 v 1, 2 1. all voltages referenced to v ss . 2. v ih may overshoot to v cc + 1.2v for pulse widths of 4.0ns with 3.3 volt, or v cc + 2.0v for pulse widths of 4.0ns (or v cc + 1.0v for 8.0ns) with 5.0 volt. additionally, v il may undershoot to -2.0v for pulse widths 4.0ns with 3.3 volt, or to -2.0v for pulse widths 4.0ns (or -1.0v for 8.0ns) with 5.0 volt. pulse widths measured at 50% points with amplitude measured peak to dc ref- erence. capacitance (t a = 25 c, v cc = 3.3v 0.3v or v cc = 5.0v 0.5v) symbol parameter min. max. units notes c i1 input capacitance (a0 - a10) 5 pf 1 c i2 input capacitance ( ras, cas, we, oe) 7 pf 1 c o output capacitance (i/o0 - i/o7) 7 pf 1 1. input capacitance measurements made with rise time shift method with cas & ras = v ih to disable output. discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 31 28h4724 sa14-4221-06 revised 4/97 dc electrical characteristics (t a = 0 to +70?c, v cc = 3.3v 0.3v or v cc = 5.0v 0.5v) symbol parameter min. max. units notes i cc1 operating current average power supply operating current ( ras, cas, address cycling: t rc = t rc min.) -50 75 ma 1, 2, 3 -60 60 i cc2 standby current (ttl) power supply standby current ( ras = cas = v ih ) 1ma i cc3 ras only refresh current average power supply current, ras only mode ( ras cycling, cas = v ih : t rc = t rc min) -50 75 ma 1, 3 -60 60 i cc4 edo (hyper page) mode current average power supply current ( ras = v il , cas, address cycling: t pc = t pc min) -50 35 ma 1, 2, 3 -60 30 i cc5 standby current (cmos) power supply standby current ( ras = cas = v cc - 0.2v) sp version 1 ma lp version 0.1 i cc6 cas before ras refresh current average power supply current, cas before ras mode ( ras, cas, cycling: t rc = t rc min) -50 75 ma 1, 3 -60 60 i cc7 self refresh current, lp version only average power supply current during self refresh cbr cycle with ras 3 t rass (min); cas held low; we = v cc - 0.2v; addresses and d in = v cc - 0.2v or 0.2v. 3.3v 200 m a 5.0v 300 i i(l) input leakage current input leakage current, any input (0.0 v in (v cc + 0.3v)), all other pins not under test = 0v -5 +5 m a i o(l) output leakage current (d out is disabled, 0.0 v out v cc ) -5 +5 m a v oh output level (ttl) output h level voltage (i out = -2.0ma for 3.3v, or i out = -5ma for 5.0v) 2.4 v cc v v ol output level (ttl) output l level voltage (i out = +2.0ma for 3.3v, or i out = +4.2ma for 5.0v) 0.0 0.4 v 1. i cc1 , i cc3 , i cc4 and i cc6 depend on cycle rate. 2. i cc1 and i cc4 depend on output loading. speci?ed values are obtained with the output open. 3. address can be changed once or less while ras =v il . in the case of i cc4 , it can be changed once or less when cas =v ih . discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram 28h4724 sa14-4221-06 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 31 ac characteristics (t a = 0 to +70?c, v cc = 3.3v 0.3v or v cc = 5.0v 0.5v) 1. an initial pause of 200 m s is required after power-up followed by 8 ras only refresh cycles before proper device operation is achieved. in case of using the internal refresh counter, a minimum of 8 cas before ras refresh cycles instead of 8 ras only refresh cycles is required. 2. ac measurements assume t t =2ns. 3. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . 4. valid column addresses are a0 through a9. read, write, read-modify-write and refresh cycles (common parameters) symbol parameter -50 -60 units notes min. max. min. max. t rc random read or write cycle time 84 104 ns t rp ras precharge time 30 40 ns t cp cas precharge time 8 10 ns t ras ras pulse width 50 10k 60 10k ns t cas cas pulse width 8 10k 10 10k ns t asr row address setup time 00 ns t rah row address hold time 10 10 ns t asc column address setup time 00 ns t cah column address hold time 8 _ 10 ns t rcd ras to cas delay time 14 37 14 45 ns 1 t rad ras to column address delay time 12 25 12 30 ns 2 t rsh ras hold time 8 10 ns t csh cas hold time 38 45 ns t crp cas to ras precharge time 55 ns t dzo oe delay time from d in 00 ns 3 t dzc cas delay time from d in 00 ns 3 t t transition time (rise and fall) 2 50 2 50 ns 4 1. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 2. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is speci?ed as a reference point only. if t rad is greater than the speci?ed t rad (max.) limit, then access time is controlled by t aa . 3. either t dzc or t dzo must be satis?ed. 4. ac measurements assume t t =2ns. discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 31 28h4724 sa14-4221-06 revised 4/97 write cycle symbol parameter -50 -60 units notes min. max. min. max. t wcs write command set up time 0 0 ns 1 t wch write command hold time 7 10 ns t wp write command pulse width 7 10 ns t rwl write command to ras lead time 7 10 ns t cwl write command to cas lead time 7 10 ns t oed oe to d in delay time 13 15 ns 2 t ds d in setup time 00 ns 3 t dh d in hold time 710 ns 3 1. t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min), the cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle. if t rwd 3 t rwd (min), t cwd 3 t cwd (min) and t awd 3 t awd (min), the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. if neither of the above sets of conditions are satisfied, the condition of the data out (at access time) is indeterminate. 2. either t cdd or t oed must be satis?ed. 3. these parameters are referenced to cas leading edge in early write cycles and to we leading edge in read-modify-write cycles. discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram 28h4724 sa14-4221-06 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 31 read cycle symbol parameter -50 -60 units notes min. max. min. max. t rac access time from ras 50 60 ns 1, 2, 3 t cac access time from cas 13 15 ns 1, 3 t aa access time from address 25 30 ns 2, 3 t oea access time from oe 13 15 ns 3 t rcs read command setup time 00 ns t rch read command hold time to cas 00 ns 4 t rrh read command hold time to ras 00 ns 4 t ral column address to ras lead time 25 30 ns t clz cas to output in low-z 00 ns 3 t off output buffer turn-off delay 13 15 ns 5, 6 t cdd cas to d in delay time 1315 ns 7 t oez output buffer turn-off delay from oe 13 15 ns 5 t oes oe setup time prior to cas 55 ns t ord oe setup time prior to ras (hidden refresh) 00 ns 1. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 2. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is speci?ed as a reference point only. if t rad is greater than the speci?ed t rad (max.) limit, then access time is controlled by t aa . 3. measured with the speci?ed current load and 100pf at v ol = 0.8v and v oh = 2.0v. 4. either t rch or t rrh must be satis?ed for a read cycle. 5. t off (max) and t oez (max) de?ne the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 6. t off is referenced from the rising edge of ras or cas, which ever is last. 7. either t cdd or t oed must be satis?ed. discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 31 28h4724 sa14-4221-06 revised 4/97 read-modify-write cycle symbol parameter -50 -60 units notes min. max. min. max. t rwc read-modify-write cycle time 110 135 ns t rwd ras to we delay time 67 79 ns 1 t cwd cas to we delay time 30 34 ns 1 t awd column address to we delay time 42 49 ns 1 t oeh oe command hold time 7 10 ns 1. t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min), the cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle. if t rwd 3 t rwd (min), t cwd 3 t cwd (min) and t awd 3 t awd (min), the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. if neither of the above sets of conditions are satisfied, the condition of the data out (at access time) is indeterminate. extended data out (hyper page) mode cycle symbol parameter -50 -60 units notes min. max. min. max. t hcas edo (hyper page) mode cas pulse width 8 10k 10 10k ns t hpc edo (hyper page) mode cycle time (read/write) 20 25 ns t hprwc edo (hyper page) mode read modify write cycle time 51 60 ns t doh data-out hold time from cas 55 ns t whz output buffer turn-off delay from we 010010 ns t wpz we pulse width to output disable at cas high 7 10 ns t cprh ras hold time from cas precharge 30 35 ns t cpa access time from cas precharge 28 35 ns 1 t rasp edo (hyper page) mode ras pulse width 50 200k 60 200k ns t oep oe precharge 55 ns t oehc oe high hold time from cas high 55 ns 1. measured with the specified current load and 100pf at v ol = 0.8v and v oh = 2.0v. discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram 28h4724 sa14-4221-06 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 31 refresh cycle symbol parameter -50 -60 units notes min. max. min. max. t csr cas setup time ( cas before ras refresh cycle) 55 ns t chr cas hold time ( cas before ras refresh cycle) 10 10 ns t wrp we setup time ( cas before ras refresh cycle) 10 10 ns t wrh we hold time ( cas before ras cycle) 10 10 ns t rpc ras precharge to cas hold time 5 5 ns self refresh cycle - low power version only symbol parameter -50 -60 units notes min. max. min. max. t rass ras pulse width during self refresh cycle 100 100 m s 1 t rps ras precharge time during self refresh cycle 89 104 ns 1 t chs cas hold time from ras rising during self refresh cycle -50 -50 ns 1, 2 t chd cas hold time from ras falling during self refresh cycle 350 350 m s 1, 2 1. when using self refresh mode, the following refresh operations must be performed to ensure proper dram operation: if row addresses are being refreshed in an evenly distributed manner over the refresh interval using cbr refresh cycles, then only one cbr cycle must be performed immediately after exit from self refresh. if row addresses are being refreshed in any other manner (ror- distributed/burst; or cbr-burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from self refresh. 2. if t rass >t chd (min) then t chd applies. if t rass t chd (min) then t chs applies. refresh symbol parameter -50 -60 units notes min. max. min. max. t ref refresh period sp version 32 32 ms 1 lp version 128 128 1. 2048 cycles. discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 31 28h4724 sa14-4221-06 revised 4/97 read cycle ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column valid data out t ras t rp t rc t cas t csh t crp t rah t asc t cah t asr t rad t rcs t dzc t clz t cac t rac hi-z hi-z t rrh : h: or l t rcd t oez hi-z t rsh t ral t dzo t aa t oea t oed t cdd cas t rch t off t oes discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram 28h4724 sa14-4221-06 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 31 write cycle (early write) t rc ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column t ras t rp t rcd t csh t crp t rah t asc t cah t asr t rad t wcs hi-z : h or l valid data in t wch t ds t dh t cas t rsh t wp cas discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 31 28h4724 sa14-4221-06 revised 4/97 write cycle (delayed write) ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column t ras t rp t rc t cas t csh t crp t rah t asc t cah t asr t rad t rwl : h or l t wp t cwl valid data in hi-z hi-z t dzo t oez t clz t ds t rcd t dh t rcs * * t oeh greater than or equal to t cwl hi-z t rsh t dzc t oea t oeh t oed cas t wrp discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram 28h4724 sa14-4221-06 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 31 read-modify-write cycle d in t oeh v ol v oh v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih t rcd t rwc t ras t csh t cas t rp t rah t asc t asr t cah t cwd t rcs t oea t rwl t cwl t wp t dh t ds t dzc t cac t clz t oed t oez t rac ras address we oe d in d out hi-z hi-z d out row column : h or l * t oeh greater than or equal to t cwl * hi-z t crp t awd t aa t rwd t rsh t rad t dzo cas discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 16 of 31 28h4724 sa14-4221-06 revised 4/97 edo (hyper page) mode read cycle t rp t hcas data out 1 data out 2 oe we ras row address column 1 column 2 column n t oea t doh t oez t clz t cac v ih v il t asr t rah t asc t asc t cah t cah t cah d out t rasp t cprh t crp t rsh t hcas t hcas t hpc t asc t csh t rad t rcs t cac t cpa t cpa t aa t aa t rac t aa hi-z : h or l t ral v ih v il v ih v il v ih v il v ih v il v oh v ol t rcd t cp t cp t rrh t rch t wp t cac data out n t off cas t oes t doh discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram 28h4724 sa14-4221-06 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 17 of 31 edo (hyper page) mode read cycle ( oe control) t rp data out 1 data out 2 oe we ras row address column 1 column 2 column n t oea t oez t clz t cac v ih v il t asr t rah t asc t asc t cah t cah t cah d out t rasp t cprh t crp t rsh t hcas t hcas t hpc t asc t csh t rad t rcs t cac t cpa t cpa t aa t aa t rac t aa hi-z : h or l t ral v ih v il v ih v il v ih v il v ih v il v oh v ol t rcd t cp t cp t rrh t rch t cac data out n t off t oea t oez t oez t oea cas t oes t hcas t oes t oehc t oep t oehc t oep t oes discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 18 of 31 28h4724 sa14-4221-06 revised 4/97 edo (hyper page) mode read cycle ( we control) t rp data out 1 data out 2 oe we ras row address column 1 column 2 column n t oea t oez t clz t cac v ih v il t asr t rah t asc t asc t cah t cah t cah d out t rasp t cprh t crp t rsh t hcas t hcas t hpc t asc t csh t rad t rcs t cac t cpa t cpa t aa t aa t rac t aa hi-z : h or l t ral v ih v il v ih v il v ih v il v ih v il v oh v ol t rcd t cp t cp t rrh t rch t cac data out n t off cas t oes t hcas t wpz t wpz t rch t rcs t rcs t rch t whz t whz discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram 28h4724 sa14-4221-06 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 19 of 31 edo (hyper page) mode early write cycle t hcas t rp ras row address we column 1 column 2 column n data in 1 data in 2 data in n t asr t rah t cah t wch t dh d in t rasp t rsh t hcas t hcas t hpc t rad t asc t asc t csh t cah t asc t cah t wch t wcs t wch t wcs t wcs t ds t ds t dh t dh t ds : h or l t cwl t rwl t wp t wp t wp oe = dont care v ih v il v ih v il v ih v il v ih v il v ih v il t rcd t cp t cp t crp cas t ral discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 20 of 31 28h4724 sa14-4221-06 revised 4/97 edo (hyper page) mode late write cycle t hcas t rp ras row address we column 1 column 2 column n oe data in 1 data in 2 data in n t asr t rah t asc t asc t asc t cah t cah t cah t cwl t wp t cwl t wp t cwl t wp t oeh t oeh t oeh t ds t dh t oed t ds t dh t oed t ds t dh d in : h or l t rasp t rsh t hcas t hcas t hpc t csh t oed hi-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t rcd t cp t cp t crp t rad t rcs t rcs t rcs t rwl cas t ral discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram 28h4724 sa14-4221-06 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 21 of 31 edo (hyper page) mode read modify write cycle address ras we oe d out d in d in d in t rp t cp t cp t asr t rad t rah t cah t asc t asc t cah t asc t cah t wp t cwl t wp t rcs t rcs t wp t cwl t rwl t cac t oeh t oeh t oeh d out d out t clz t clz t oed t oed t dh t dh t clz t oed t dh d in d out : h or l hi-z hi-z t rasp t cas t hprwc t cas t ral t awd t cwd t aa t cpa t aa t awd t cwd t rwd t awd t cwd t rcs t rac t aa t oea t oea t cac t cac t oea t oez t oez t ds t ds t ds column 1 row column 2 column n t csh t oez v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il t rcd t cas t crp t cpa cas discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 22 of 31 28h4724 sa14-4221-06 revised 4/97 edo (hyper page) mode read and write cycle t rp we t rcd t hcas t cp t cp ras row address column 1 column 2 column n oe data out data out t asr t rah t asc t asc t cah t cah data in t rch t cac t oea t cac t clz t doh t whz t oez t ds t dh d in d out : h or l t rasp t rsh t hcas t hcas t hpc t rad t csh t asc t ral t cah t wch t wcs t rcs t aa t cpa hi-z hi-z t rac t aa t wp v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il t crp cas discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram 28h4724 sa14-4221-06 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 23 of 31 ras only refresh cycle ras v ih v il v ih v il address v ih v il d out v oh v ol row t ras t rp t rc t rah t asr hi-z : h or l note: we, oe and d in are h or l t rpc t crp cas discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 24 of 31 28h4724 sa14-4221-06 revised 4/97 cas before ras refresh cycle ras v ih v il v ih v il we v ih v il d in v oh v ol t ras t rp oe v ih v il d out v oh v ol hi-z : h or l t off t oez hi-z t oed t chr rc t t wrh t wrp t note: address is h or l rpc t cp t cdd cas t rpc t csr t wrh t wrp t csr discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram 28h4724 sa14-4221-06 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 25 of 31 hidden refresh cycle (read) ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column valid data out t ras t ras t rp t rc t crp t rah t asc t cah t asr t rad t rcs t dzc t oed t oez t cdd t clz t cac t rac hi-z hi-z : h or l t rp t chr rsh t rcd t t rrh t wrp t wrh t rc t dzo t ral t off cas t oea t ord t aa hi-z discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 26 of 31 28h4724 sa14-4221-06 revised 4/97 hidden refresh cycle (write) ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column valid data t ras t ras t rp t rc t crp t rah t asc t cah t asr hi-z : h or l t rp t chr rsh t t ds t dh t wch wcs t t wrp t wrh t rc t wp t rcd cas discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram 28h4724 sa14-4221-06 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 27 of 31 self refresh cycle (sleep mode) - low power version only ras v ih v il v ih v il we v ih v il t rass t rps t crp d out v oh v ol hi-z : h or l t off t cp t csr t wrh t wrp t rpc cas t chd t chs notes: 1. address and oe are h or l 2. once ras (min) is provided and ras remains low, the dram will be in self refresh, commonly known as sleep mode. 3. if t rass > t chd (min) then t chd applies. if t rass t chd (min) then t chs applies. discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 28 of 31 28h4724 sa14-4221-06 revised 4/97 package dimensions (400 mil; 28/28 lead; thin small outline package) note: all dimensions are in millimeters; package diagrams are not drawn to scale 1.27 basic 10.16 18.41 11.76 0.20 0.10 0.125 detail a lead #1 0.95 ref +0.075 -0.005 detail a 0.25 basic gage plane 0.5 0.1 0.05 1.20 max +0.10 -0.00 1.00 0.05 seating plane 0.40 0.10 0.10 0.10 discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram 28h4724 sa14-4221-06 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 29 of 31 package dimensions (300 mil; 28/28 lead; small outline j-lead) note: all dimensions are in millimeters; package diagrams are not drawn to scale 1.27 basic 6.78 basic 18.41 0.10 7.62 8.51 0.203 - 0.025 + 0.05 0.76 min 2.08 min 3.50 0.25 lead #1 seating plane 0.420 - 0.014 + 0.09 0.690 - 0.03 + 0.12 pin #1 id discontinued (9/98 - last order; 3/99 last ship)
ibm0117805 IBM0117805M ibm0117805b ibm0117805p 2m x 8 11/10 edo dram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 30 of 31 28h4724 sa14-4221-06 revised 4/97 revision log revision contents of modi?cation 11/15/95 initial release 12/10/95 1. the low power and standard power specifications were combined. es# 43g9060 and es# 28h4724 were combined into es# 28h4724. 2. added die rev e part numbers. 3. a -6r speed sort was added, with the following differences over the -60 speed sort: - t cac was increased from 15ns to 17ns for the -6r speed sort - t rcd (max) was decreased from 45ns to 43ns for the -6r speed sort. - t cwd was increased from 34ns to 36ns for the -6r speed sort. - t oea was increased from 15ns to 17ns for the -6r speed sort. 4. t chd was added to the self refresh cycle with a value of 350 m s for all speed sorts. 5. the self refresh timing diagram was changed to allow cas to go high t chd (350 m s) after ras falls entering a self refresh. 6. the cbr timing diagram was changed to allow cas to remain low for back-to-back cbr cycles. 7. we for the hidden refresh write cycle in the truth table was changed from l to h. 09/01/96 1. i cc2 was changed from 2ma to 1ma. 2. i i(l) and i o(l) were altered from +/- 10ua to +/- 5ua. 3. t rc was changed from 89ns to 84ns for the -50 speed sort. 4. t csh changed from 45ns to 38ns, 50ns to 45ns, and 55ns to 50ns for the -50, -60, and -70 speed sorts, respec- tively. 5. t t was initially at a max of 30ns. it has been modified to 50ns for all speed sorts. 6. t cpa was decreased from 30ns to 28ns for the -50 speed sort. 7. t rasp max of 125k was raised to 200k for all speed sorts. 8. t oep was changed from 10ns to 5ns for all speed sorts. 9. t oehc was also lowered from 10ns to 5ns for all speed sorts. 10. t rp was changed from 35ns to 30ns for the -50 speed sort. 03/19/97 1. we for the hidden refresh write cycle in the truth table was changed from h to l ? h. 2. t oed was moved from the common parameters table to the write cycle parameters table. 3. t rwc for the -50 part was changed from 115ns to 100ns. 4. the note implementing we at ras time during a read or write cycle is optional. doing so will facilitate com- patibility with future edo drams. was removed from all of the read and write timing diagrams. 5. t odd in the cas before ras timing diagram was renamed t oed . 6. the 300mil 28 pin soj package was added to the spec. 7. the -6r and -70 speed sorts and timings were removed. 8. i cc1 , i cc3 , i cc6 for the -50 speed sort were reduced from 100ma to 75ma. 9. i cc4 for the -50 speed sort was reduced from 60ma to 35ma. 10. i cc1 , i cc3 , i cc6 for the -60 speed sort were reduced from 90ma to 60ma. 11. i cc4 for the -60 speed sort was reduced from 50ma to 30ma. 04/23/97 1. i cc5 was changed from 200 m a to 100 m a for the low power die rev f parts. discontinued (9/98 - last order; 3/99 last ship)
intern ational business machines corp.1997 printed in the united states of america all rights reserved ibm and the ibm logo are registered trademarks of the ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility or liability for any use of the information contained herein. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including, but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document . for more information contact your ibm microelectronics sales representative or visit us on world wide web at http://www.chips.ibm.com ibm microelectronics manufacturing is iso 9000 compliant. a discontinued (9/98 - last order; 3/99 last ship)

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